PUBLICATIONSPUBLICATONS

K. Asano, M. Iwamoto, and Y. Watanabe, “Protecting against Partial Key Exposure in Key-Insulated Encryption,” IEICE Transactions on Fundamentals, Vol. 108, pp. 1139–1151, 2025.

C. J. Clarke, Y. Kasashima, K. Sato, and Y. Watanabe, “SoK: Searchable Encryption with Differential Privacy,” APKC 2025, pp. 25–33, 2025.

T. Ono, S. Ruangwises, Y. Abe, K. Hatsugai, and M. Iwamoto, “Single-Shuffle Physical Zero-Knowledge Proof for Sudoku Using Interactive Inputs,” APKC 2025, pp. 1–8, 2025.

K. Sato, T. Amada, K. Asano, Y. Watanabe, M. Iwamoto, and K. Ohta, “Revisiting Relations of Security Notions in Searchable Encryption,” APKC 2025, pp. 17–24, 2025.

K. Asano, N. Attrapadung, K. Hara, K. Hashimoto, and Y. Watanabe, “Key Revocation in Registered Attribute-Based Encryption,” PKC 2025, pp. 102–133, 2025.

T. Tanaka, K. Sawada, Y. Watanabe, and M. Iwamoto, “Covert Vehicle Misguidance and Detection: A Hypothesis Testing Game over Continuous-Time Dynamics,” ACC 2025, 2025.

K. Asano and Y. Watanabe, “Updatable Public Key Encryption with Strong CCA Security: Security Analysis and Efficient Generic Construction,” CT-RSA 2025, pp. 223–246, 2025.

Y. Watanabe, K. Asano, H. Hirata, T. Ono, M. Yang, M. Iwamoto, Y. Li, and Y. Hara, “PSYLOCKE: Provably Secure Logic Locking with Practical Efficiency,” USENIX Security 2025, Poster, Seattle, WA, USA, 2025.

Mayu Nomura, Daiki Miyahara, Yang Li, and Kazuo Sakiyama, “Functional Verification and Authenticity Validation of Logic-Locked Circuits Using Side-Channel Authentication Techniques,” NEWCAS 2025, Poster, 2025.

Yuto Takino, Daiki Miyahara, Yang Li, and Kazuo Sakiyama, “A Security Evaluation Model for LUT-Based Logic Locking,” NEWCAS 2025, Poster, 2025.

APKC 2025 Best Paper Award (T. Ono, S. Ruangwises, Y. Abe, K. Hatsugai, and M. Iwamoto), “Single-Shuffle Physical Zero-Knowledge Proof for Sudoku Using Interactive Inputs,” APKC 2025, 2025.

T. Tanaka, K. Sawada, Y. Watanabe, and M. Iwamoto, “Covert Vehicle Misguidance and Its Detection: A Hypothesis Testing Game over Continuous-Time Dynamics,” IEEE Control Systems Letters, vol. 8, pp. 2889–2894, IEEE, 2024.

T. Ichioka, Y. Watanabe, and Y. Hara, “PreLock: Precision Locking for Protecting Embedded Processor,” AsianHOST 2024, 2024. (To appear)

Y. Kasashima, K. Sugimoto, Y. Watanabe and M. Iwamoto, “Towards Defining a New Security Model for Private Set Intersection,” IWSEC 2024, Poster, Kyoto, Japan, 2024.

T. Ono, H. Hirata, K. Asano, M. Yang, Y. Watanabe, Y. Hara, and M. Iwamoto, “Towards Efficient Logic Locking with Provable Security,” IWSEC 2024, Poster, Kyoto, Japan, 2024.

K. Sugimoto, Y. Watanabe and M. Iwamoto, “Multi-Party Computation for Large-Scale Parties in the Real World,” IWSEC 2024, Poster, Kyoto, Japan, 2024.

M. Iwamoto, “Information-Theoretic Perspectives for Simulation-Based Security in Multi-Party Computation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.EA107-A, no.3, pp.360–372, IEICE, 2024. [Invited Paper]